Concurrent Bist Synthesis and Test Scheduling Using Genetic Algorithms
نویسندگان
چکیده
This paper presents a new efficient method for concurrent BIST synthesis and test scheduling in high-level synthesis. The method maximizes concurrent testing of modules while performing the allocation of functional units, test registers, and multiplexers. The method is based on a genetic algorithm that efficiently explores the testable design space. The method was implemented using C++ on a Linux workstation. Several benchmark examples have been implemented and favorable design comparisons are reported.
منابع مشابه
BIST hardware synthesis for RTL data paths based on testcompatibility classes
New BIST methodology for RTL data paths is presented. The proposed BIST methodology takes advantage of the structural information of RTL data path and reduces the test application time by grouping same-type modules into test compatibility classes (TCCs). During testing, compatible modules share a small number of test pattern generators at the same test time leading to significant reductions in ...
متن کاملTest Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint
This paper presents a novel approach for test generation and test scheduling for multi-clock domain SoCs. A concurrent hybrid BIST architecture is proposed for testing cores. Furthermore, a heuristic for selecting cores to be tested concurrently and order of applying test patterns is proposed. Experimental results show that the proposed heuristics give us an optimized method for multi clock dom...
متن کاملTest Time versus Design-for-Test Resources in Mixed Signal Systems
Functional macro testing of analog subsystems is providing a reasonable approach to testing in mixed signal systems. This allows the partitioning of the analog from digital components. Two approaches emerge: analog test bus and Built-In-Self-Test (BIST). Design-for-Test (DFT) issues arise in both approaches which include additional circuitry for control and observation. This additional circuit ...
متن کاملPower conscious test synthesis and scheduling for BIST RTL data paths
Previous research has outlined that power dissipated during test application is substantially higher than during functional operation, which leads to loss of yield and decreases reliability. This paper shows for the first time how power is minimized in BIST RTL data paths by using power conscious test synthesis and test scheduling. According to the necessity for achieving the required test effi...
متن کاملGENETIC AND TABU SEARCH ALGORITHMS FOR THE SINGLE MACHINE SCHEDULING PROBLEM WITH SEQUENCE-DEPENDENT SET-UP TIMES AND DETERIORATING JOBS
This paper introduces the effects of job deterioration and sequence dependent set- up time in a single machine scheduling problem. The considered optimization criterion is the minimization of the makespan (Cmax). For this purpose, after formulating the mathematical model, genetic and tabu search algorithms were developed for the problem. Since population diversity is a very important issue in ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2004